The present invention pertains to a process for manufacturing electronic devices comprising nonvolatile memory cells with dimensional control of the floating gate regions.
Devices using nonvolatile memories of the EEPROM type, such as smart cards, complex microcontrollers and mass storage devices requiring programmability of the single byte, call for increasingly higher levels of performance and reliability.
In practice, from the technological standpoint, this means that it is necessary to get high levels of performance (i.e., increasingly thinner tunnel oxides, ever more reduced programming voltages, increasingly greater current driving capability of the cells) to coexist with an extremely high reliability: one hundred thousand programming cycles and retention of the stored charge for at least ten years are by now considered the minimum requisites for the acceptance of this type of product on the market.
According to the above, it is necessary to develop new manufacturing processes and new geometries that are able to eliminate some of the critical aspects typical of memories, thus increasing their intrinsic reliability without reducing their performance, both for embedded applications (i.e., wherein the memory cells are associated to special electronic devices) and for stand-alone applications (i.e., wherein the device is merely a nonvolatile memory).
The embodiments of the present invention provide a manufacturing process that enables the critical aspects of known processes to be reduced.
According to embodiments of the present invention, there are provided a process for manufacturing electronic devices having nonvolatile memory cells and an electronic device comprising nonvolatile memory cells, the process includes defining an active area in a substrate of semiconductor material; forming a first insulating region on top of the active area; depositing a first dielectric material on top of the substrate, the first dielectric material comprising a tunnel area; and forming a floating gate region on top of the first dielectric material layer and on top of the first insulating region, which includes depositing a first semiconductor material layer on top of the dielectric material layer and the first insulating region and selectively removing the first semiconductor material layer using a floating gate mask having an outer delimiting side, an opening with an internal delimiting side facing the outer delimiting side at a preset distance and removing the first semiconductor material layer at the side of the external delimiting side and below the opening to form a hole in the floating gate region and filling the hole with an electrically insulating material; forming a second insulating region surrounding the floating gate region; forming a control gate region on top of the floating gate region; and forming conductive regions in the active area.